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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:50:12 10/06/2013 
-- Design Name: 
-- Module Name:    unsigned_32_comparator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.ALL;
use IEEE.NUMERIC_STD.ALL;

entity slt is
	PORT (
	A : in STD_LOGIC_VECTOR(31 downto 0); -- Operand 1
	B : in STD_LOGIC_VECTOR(31 downto 0); -- Operand 2
	
	D : out STD_LOGIC -- Out result
	);
end slt;

architecture Behavioral of slt is
	component subtractor is
		PORT (
		OP: in STD_LOGIC_VECTOR(1 downto 0); -- Op-code, 0 for add, 1 for sub

		A : in STD_LOGIC_VECTOR(31 downto 0); -- Operand 1
		B : in STD_LOGIC_VECTOR(31 downto 0); -- Operand 2
		C : in STD_LOGIC_VECTOR(31 downto 0); -- Carry/ borrow
		
		D : out STD_LOGIC_VECTOR(31 downto 0); -- Out result
		
		F_O : out STD_LOGIC; -- Overflow flag, assert when signed arithmetic mode
		F_C : out STD_LOGIC; -- Carry flag, assert when unsigned arithemtic mode
		F_Z : out STD_LOGIC  -- Zero flag, assert when result is zero
	);
	end component;

	signal sub_op : STD_LOGIC := '1';
	signal carry : STD_LOGIC := '0';
	signal sub_result : STD_LOGIC_VECTOR(31 downto 0);
	signal flago, flagc, flagz : STD_LOGIC;
begin
	subtractor_guy : subtractor
	port map
	(
		OP => sub_op,

		A => A,
		B => B,
		C => carry,

		D => sub_result,

		F_O => flago,
		F_Z => flagz,
		F_C => flagc
	);


	process (A, B)
	begin
		if (A(31) > B(31)) then -- if A is negative and B is positive
			D <= '1';
		elsif (A(31) = B(31)) then
			D <= sub_result(31);
		end if;
	end process;
end Behavioral;